嶄冷 訓勉ナカタケ シゲトシShigetoshi Nakatake
侭奉 | ‐僥何/秤鵐轡好謄犢ぱЭ ‐寄僥垪/秤鷙ぱ好 蛮栽システムコ`ス |
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叨/兆 | 縮娩 | |
僥了娩嚥Cv | 鴬平┨ぱВ|奨垢I寄僥 | |
毅輝親朕 | 僥何 ?アルゴリズムとデ`タ夛 ?鹿e指揃O ?秤鵐瓮妊ア垢僥gY及IVFPGAO 寄僥垪 ?VLSI麗尖O ?d鬚LSIO處 ?VLSI麗尖O蒙 |
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待s | 1992定3埖|奨垢I寄僥 垢僥何 沂徨垢僥親 怱I 1994定3埖艮炎枠極親僥室g寄僥垪寄僥 秤鷽苫а仂真 秤鵐轡好謄猾好 鴬平念豚n殻俐阻 1996定4埖|奨垢I寄僥 垢僥何 沂徨垢僥親 廁返 彭販 1999定1埖|奨垢僥寄僥 鴬平┨ぱВ僥了函誼 1999定4埖艮云砥欖麪 忽Hh廠垢僥何O崔篳 v 彭販 2001定4埖艮云砥殃仭寄僥 忽Hh廠垢僥何 秤鵐瓮妊ア垢僥親 彈縮娩 彭販 F壓に崛る |
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T蛍勸 | ?VLSI CADアルゴリズム ?VLSI麗尖O室g ?アナログ?ディジタル詞dLSIO室g |
IB初
[ICCAD95] H.Murata, K.Fujiyoshi, S. Nakatake, Y.Kajitani, ^Rectangle-Packing Based on Module Placement ̄, ICCAD95, pp.472-479, 1995.
[TCAD96] VLSI H.Murata, K.Fujiyoshi, S.Nakatake, Y.Kajitani, ^Module Placement Based on Rectangle-Packing by the Sequence-Pair ̄, IEEE Trans. on CAD, vol.15, No.12, pp.1518-1524, 1996.
[ASPDAC02] Y.Kubo, S.Nakatake, Y.Kajitani, M.Kawakita, ^Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts ̄, ASPDAC02, pp.467-472, 2002.
[ASPDAC04] T.Nojima, X.Zhu, Y.Takashima, S.Nakatake, Y.Kajitani, ^Multi-Level Placement with Circuit Schema Based Clustering in Analog IC Layouts ̄, ASPDAC04, pp.406-411, 2004.
[GLSVLSI04] T.Nojima, X.Zhu, Y.Takashima, S.Nakatake, Y.Kajitani, ^A Device-Level Placement with Multi-Directional Convex Clustering ̄, GLSVLSI04, pp.196-201, 2004.
[IEICE04] T.Nojima, X.Zhu, Y.Takashima, S.Nakatake, Y.Kajitani, ^A Device-Level Placement with Schema Based Clusters in Analog IC Layouts ̄, IEICE Trans. on Fundamentals, Vol.E87-A, No.12, pp.3301-3308, 2004.
[IEICE06] N. Fu, S. Nakatake, Y. Takashima, Y. Kajitani, ^The Oct-Touched Tile: A New Architecture for Shape-Based Routing  ̄, IEICE Trans. on Fundamentals, Vol.E89-A, No.2, pp.448-445, 2006 .
[ISVLSI06a] N Fu, S. Nakatake, M. Mineshima, ^Multi-SP: A Representation with United Rectangles for Analog Placement and Routing ̄, ISVLSI06, pp.38-43, 2006.
[ISVLSI06b] T.Nojima, S.Nakatake, T.Fujimura, K.Okazaki, Y.Kajitani, N.Ono, ^Adaptive Porting of Analog IPs with Reusable Conservative Properties ̄, ISVLSI06, pp.18-23, 2006.
[ASPDAC07] S.Nakatake, ^Structured Placement with Topological Regularity Evaluation ̄, ASPDAC07, pp.215-220, 2007.
[ASPDAC08] Q.Dong, S.Nakatake, ^Constraint-Free Analog Placement with Topological Symmetry Structure ̄, ASPDAC08, pp.186-191, 2008.
鞭Y伏鬚吋瓮奪皐`ジ
パソコンや亊。などの晒u瞳には、いずれも寄ト鹿e指揃LSIが廾野されており、Nかで芦畠な芙氏をるためには、互來嬬なLSIの_kが之かせないものなっています。まずは、櫃砲茲辰嘛するモノにd龍をもってください。それを泌採にOし、り貧げていくかを寄僥で僥びましょう。
二Iメッセ`ジ
アナログ?ディジタル詞dLSIの徭嘖O室gについて冩梢を佩っています。蒙に、アナログO、式びその徭嘖O室gが恷除のテ`マになっています。